There is renewed interest in using programmable integrated circuits (ICs), such as field programmable gate arrays (FPGAs), for deploying neural networks. Present FPGA implementations of neural networks focus on floating point or fixed-point multiply-accumulate typically based on a systolic array architecture. Recently, it has been demonstrated that even large and modern machine learning problems can be solved with neural networks using binary representations for weights and activations while achieving high accuracy. However, implementations of binary neural networks have heretofore been constrained to software.